1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a blanket protection layer to protect a metal hard mask layer during lithography reworking processes.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
In general, the formation of integrated circuit products involves performing a detailed sequence, i.e., a detailed process flow, of many different process operations, such as, for example, deposition processes, etching processes, ion implantation processes, chemical mechanical polishing (CMP) processes, photolithography processes, heating processes, etc., to manufacture the device. Such process operations are performed, more or less, on a layer-by-layer basis until the device is completed. As indicated, photolithography is one of the basic processes used in manufacturing integrated circuit products. A typical photolithography process generally involves the steps of: (1) applying a layer of photoresist above a wafer, typically accomplished by a spin-coating process; (2) pre-baking (or soft-baking) the layer of photoresist at a temperature of approximately 90-120° C. to reduce the level of solvents in the layer of photoresist and to improve the adhesion characteristics of the photoresist; (3) performing an exposure process, wherein a so-called “stepper tool” is used to project a pattern defined in a reticle onto the layer of photoresist to thereby create a latent image of the reticle pattern in the layer of photoresist; (4) performing a post-exposure bake process on the layer of photoresist at a temperature approximately 5-15° C. higher than the pre-bake process; (5) performing a so-called “develop” process to turn the latent image in the layer of photoresist into the final resist image; and (6) performing a post-bake process (or hard-bake) at a temperature of approximately 125-160° C. to remove residual solids and to improve adhesion of the patterned photoresist mask layer. These process steps are well known to those skilled in the art and, thus, will not be described herein in any greater detail. Various process operations, such as etching or ion implantation processes, may then be performed on an underlying layer of material or substrate through the patterned photoresist mask layer.
However, as noted above, in recent years, device dimensions and pitches have been reduced in size to the point where existing photolithography tools, e.g., 193 nm wavelength photolithography tools, have difficulty forming such features to the desired degree of accuracy. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as double patterning or double patterning technology (DPT). In general, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively enables the printing of even smaller features than would otherwise be possible using a single mask using existing photolithography tools. There are several double patterning techniques employed by semiconductor manufacturers. From the foregoing, it should be clear that lithography operations must be performed very precisely to form modern integrated circuit products, as even small errors can result in integrated circuit products or transistors that do not function as intended and/or, in a worst-case situation, are completely inoperative.
FIGS. 1A-1D depict one illustrative prior art masking system that may be employed in manufacturing a variety of different features on an integrated circuit product 10. As shown therein, the product 10 is comprised of a layer of insulating material 12, a hard mask layer 14 comprised of a metal (e.g., TiN having a thickness of about 15 nm) or a metal-containing alloy, an optical planarization layer (OPL) 16, a so-called anti-reflective coating (ARC) layer 18 and a patterned photoresist mask layer 20 having a plurality of openings 22 defined therein. FIG. 2B depicts the product after a plurality of etching processes have been performed that stops on the hard mask layer 14. In general, at this point, the patterned layers 16, 18 and 20 represent one embodiment of a patterned etch mask 21 that will be used to pattern the underlying hard mask layer 14. Given the importance of accuracy in forming integrated circuit products, after the patterned etch mask 21 is initially formed and the hard mask layer 14 is exposed, the accuracy of the position and location of the patterned etch mask 21 relative to underlying layers or structures is checked. In the event that it is misaligned, i.e., not correctly positioned in terms of the location of the openings 22 relative to various other underlying layers, structures or markers on the product, the patterned etch mask 21 must be “reworked”, i.e., it must be completely removed and the process must start all over again to form a properly positioned patterned etch mask 21 before etching through the hard mask layer 14. In practice, after it has been confirmed that a correctly positioned and located patterned etch mask 21 has been formed above the hard mask layer 14, the hard mask layer 14 is patterned by performing an etching process through the properly positioned patterned etch mask 21. Thereafter, the patterned etch mask 21 will be stripped and an opening or trench (not shown) will be formed by performing an etching process through the patterned hard mask layer 14.
FIG. 1C depicts the product 10 after the illustrative patterned etch mask 21 has been removed. In the depicted example, removing the patterned etch mask 21 would typically involve (1) performing a plasma-based ashing process to remove the patterned photoresist mask layer 20; (2) performing a wet cleaning process using, for example, a dilute hydrofluoric acid (DHF) to strip the ARC layer 18; (3) performing another plasma-based process (using N2 and H2) to remove the OPL layer 16; and (4) performing a water rinse process in an attempt to remove residual materials from above the surface of the hard mask layer 14. Unfortunately, as depicted in FIG. 1C, the above-described process operations performed to remove the patterned etch mask 21 results in defects 17 in or on the surface of the hard mask layer 14. In some cases, the defects 17 may be residual portions of the OPL layer 16 positioned on the surface of the hard mask layer 14. In other cases, the defects 17 may be actual defects, e.g., gouges, etc., formed in the surface of the hard mask layer 14. The number, size and location of such defects 17 may vary depending upon the particular application.
FIG. 1D provides an illustrative example of the problems that may result from the presence of such defects 17. More specifically, FIG. 1D depicts the device 10 after another or “reworked” patterned etch mask 21A has been formed above the hard mask layer 14. The reworked patterned etch mask 21A is comprised of an optical planarization layer 16A, an ARC layer 18A and a patterned photoresist mask layer 20A having a plurality of openings 22A defined therein. In this example, the reworked patterned etch mask 21A has been formed such that it is correctly positioned on the product 10. However, the presence of the defects 17 within the openings 22A causes the patterning of the hard mask layer 14 to be less accurate than desirable and may result in the transfer of the pattern defined by the reworked patterned etch mask 21A to the hard mask layer 14 being incomplete. As a result, the formation of the features in the layer of insulating material 12 may also suffer from such inaccuracies. Moreover, there are a limited number of times that the hard mask layer 14 may be subjected to such reworking processes, e.g., 3-4 times, depending upon the application, without the hard mask layer 14 becoming so degraded that it is no longer useful for its intended purpose.
The present disclosure is directed to various methods of forming a blanket protection layer to protect a metal hard mask layer during lithography reworking processes that may avoid, or at least reduce, the effects of one or more of the problems identified above.